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The BOUNDARY SCAN register is a special case of a data register. It allows circuit-board interconnections to be tested, external COMPONENTS tested, and the STATE of CHIP digital I/Os to be sampled.

The boundary scan register is a special case of a data register. It allows circuit-board interconnections to be tested, external components tested, and the state of chip digital I/Os to be sampled.

The test-data REGISTERS are USED to set the INPUTS of modules to be tested, and to collect the RESULTS of RUNNING tests.

The test-data registers are used to set the inputs of modules to be tested, and to collect the results of running tests.

The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK and TMS signals. It PROVIDES signals that control the TEST data registers, and the instruction register. These include serial-shift clocks and UPDATE clocks.

The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK and TMS signals. It provides signals that control the test data registers, and the instruction register. These include serial-shift clocks and update clocks.

The test ARCHITECTURE consists of:

• The TAP INTERFACE pins
• A set of test-data registers
• An INSTRUCTION register
• A TAP controller

The test architecture consists of:

The Test Access PORT (TAP) is a definition of the INTERFACE that needs to be included in an IC to make it capable of being included in boundary-scan architecture.

The port has four or five single bit connections, as follows:

• TCK (The Test Clock Input)
• TMS (The Test MODE Select)
• TDI (The Test Data Input)
• TDO (The Test Data Output)

 It also has an optional SIGNAL:

• TRST*(The Test RESET Signal)

The Test Access Port (TAP) is a definition of the interface that needs to be included in an IC to make it capable of being included in boundary-scan architecture.

The port has four or five single bit connections, as follows:

 It also has an optional signal:

The increasing complexity of boards and the movement to technologies like multichip modules and surface-mount technologies resulted in system DESIGNERS agreeing on a UNIFIED scan-based METHODOLOGY for testing CHIPS at the board. This is called BOUNDARY scan.

The increasing complexity of boards and the movement to technologies like multichip modules and surface-mount technologies resulted in system designers agreeing on a unified scan-based methodology for testing chips at the board. This is called boundary scan.

• REGULAR LOGIC ARRAYS 
• MEMORIES 
• RANDOM logic

A popular method of testing for bridging FAULTS is called IDDQ or current supply monitoring. This relies on the fact that when a COMPLEMENTARY CMOS logic gate is not switching, it DRAWS no DC current. When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow.

A popular method of testing for bridging faults is called IDDQ or current supply monitoring. This relies on the fact that when a complementary CMOS logic gate is not switching, it draws no DC current. When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow.

SIGNATURE analysis can be merged with the SCAN technique to create a structure known as BILBO- for Built in LOGIC Block Observation.

Signature analysis can be merged with the scan technique to create a structure known as BILBO- for Built in Logic Block Observation.

• SIGNATURE ANALYSIS and BILBO 
• MEMORY self-test 
• Iterative logic array TESTING

The CIRCUIT is level-sensitive. Each REGISTER may be converted to a serial SHIFT register.

The circuit is level-sensitive. Each register may be converted to a serial shift register.

• LEVEL sensitive scan DESIGN 
• SERIAL scan 
• PARTIAL serial scan 
• PARALLEL scan

• Partitioning LARGE sequential circuits 
• ADDING test points 
• Adding MULTIPLEXERS 
• Providing for easy state RESET

• AD HOC TESTING 
• Scan-based APPROACHES
• Self-test and built-in testing

An APPROACH to fault analysis is known as fault sampling. This is used in CIRCUITS where it is impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be statistically INFERRED from the number of faults that are DETECTED in the fault set and the size of the set. The randomly selected faults are unbiased. It will determine whether the fault coverage exceeds a desired LEVEL.

An approach to fault analysis is known as fault sampling. This is used in circuits where it is impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be statistically inferred from the number of faults that are detected in the fault set and the size of the set. The randomly selected faults are unbiased. It will determine whether the fault coverage exceeds a desired level.

• PARALLEL SIMULATION 
• CONCURRENT simulation

Fault GRADING consists of two steps. FIRST, the node to be faulted is selected. A SIMULATION is RUN with no faults inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the test vector set is applied. If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped.

Fault grading consists of two steps. First, the node to be faulted is selected. A simulation is run with no faults inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the test vector set is applied. If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped.

The total number of NODES that, when SET to 1 or 0, do result in the DETECTION of the fault, divided by the total number of nodes in the circuit, is called the percentage-fault coverage.

The total number of nodes that, when set to 1 or 0, do result in the detection of the fault, divided by the total number of nodes in the circuit, is called the percentage-fault coverage.

The CONTROLLABILITY of an internal circuit NODE WITHIN a chip is a measure of the ease of SETTING the node to 1 or 0 states.

The controllability of an internal circuit node within a chip is a measure of the ease of setting the node to 1 or 0 states.

The observability of a particular INTERNAL circuit NODE is the degree to which ONE can OBSERVE that node at the outputs of an integrated circuit.

The observability of a particular internal circuit node is the degree to which one can observe that node at the outputs of an integrated circuit.

With this MODEL, a faulty gate INPUT is modeled as a “stuck at zero” or “stuck at one”. These FAULTS most frequently OCCUR DUE to thin -oxide shorts or metal-to-metal shorts.

With this model, a faulty gate input is modeled as a “stuck at zero” or “stuck at one”. These faults most frequently occur due to thin -oxide shorts or metal-to-metal shorts.

• Stuck-At FAULTS.
• Short-Circuit and Open-Circuit Faults.

FAULT model is a model for how faults occur and their IMPACT on circuits.

Fault model is a model for how faults occur and their impact on circuits.

• I/O LEVEL TEST 
• SPEED test 
• IDD test

• NODES SHORTED to POWER or ground 
• Nodes shorted to each other 
• Inputs floating/outputs DISCONNECTED

• Layer-to-layer SHORTS 
• DISCONTINUOUS WIRES 
• Thin-oxide shorts to SUBSTRATE or WELL

Manufacturing TESTS verify that every gate and REGISTER in the chip functions correctly. These tests are used after the chip is manufactured to verify that the SILICON is intact.

Manufacturing tests verify that every gate and register in the chip functions correctly. These tests are used after the chip is manufactured to verify that the silicon is intact.

Functionality TESTS verify that the chip performs its intended function. These tests assert that all the gates in the chip, ACTING in concert, ACHIEVE a desired function. These tests are USUALLY used early in the DESIGN cycle to verify the functionality of the circuit.

Functionality tests verify that the chip performs its intended function. These tests assert that all the gates in the chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify the functionality of the circuit.

• FUNCTIONALITY TESTS 
• MANUFACTURING tests

• At the WAFER LEVEL 
• At the packaged-chip level 
• At the BOARD level 
• At the SYSTEM level 
• In the FIELD

• DESIGN entry 
• Logic SYNTHESIS System partitioning 
• PRE layout simulation. 
• Floor PLANNING 
• PLACEMENT 
• Routing
• Extraction 
• Post layout simulation

In a PAL, the device is programmed by changing the characteristics if the SWITCHING ELEMENT. An alternative WOULD be to program the ROUTING.

In a PAL, the device is programmed by changing the characteristics if the switching element. An alternative would be to program the routing.

The logic cells in a gate-array LIBRARY are OFTEN CALLED macros.

The logic cells in a gate-array library are often called macros.

• Architectural or FUNCTIONAL LEVEL
• Register Transfer-level (RTL)
• LOGIC level
• CIRCUIT level

An antifuse is normally high resistance (>100MW). On application of appropriate programming VOLTAGES, the antifuse is changed PERMANENTLY to a low-resistance structure (200-500W).

An antifuse is normally high resistance (>100MW). On application of appropriate programming voltages, the antifuse is changed permanently to a low-resistance structure (200-500W).

The programming of PALS is done in three main WAYS:

• FUSIBLE links
• UV – erasable EPROM
• EEPROM (EePROM) – ELECTRICALLY Erasable Programmable ROM

The programming of PALs is done in three main ways:

A field PROGRAMMABLE gate ARRAY (FPGA) is a programmable logic DEVICE that supports IMPLEMENTATION of relatively large logic circuits. FPGAS can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000 equivalent gates.

A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000 equivalent gates.

2V10 I/O cell consists of:

1. A REGISTER 
2. An output 4:1 MUX 
3. A tristate BUFFER 
4. A 2:1 input mux 

It has the following characteristics: 

• 12 inputs 
• 10 I/Os 
• Product time 9 10 12 14 16 14 12 10 8 
• 24 pins

2V10 I/O cell consists of:

It has the following characteristics: 

Channeled GATE Array: Only the interconnect is customized. The interconnect uses predefined spaces between rows of base cells. ROUTING is done using the spaces. Logic density is less

CHANNEL less Gate Array: Only the top few mask LAYERS are customized. No predefined AREAS are set aside for routing between cells. Routing is done using the area of transistors unused. Logic density is higher.

Channeled Gate Array: Only the interconnect is customized. The interconnect uses predefined spaces between rows of base cells. Routing is done using the spaces. Logic density is less

Channel less Gate Array: Only the top few mask layers are customized. No predefined areas are set aside for routing between cells. Routing is done using the area of transistors unused. Logic density is higher.

A cell-based ASIC (CBIC) uses predesigned logic cells known as standard cells. The standard cell AREAS also CALLED fle4xible BLOCKS in a CBIC are built of rows of standard cells. The ASIC designer defines only the placement of standard cells and the interconnect in a CBIC. All the MASK layers of a CBIC are customized and are unique to a particular customer.

A cell-based ASIC (CBIC) uses predesigned logic cells known as standard cells. The standard cell areas also called fle4xible blocks in a CBIC are built of rows of standard cells. The ASIC designer defines only the placement of standard cells and the interconnect in a CBIC. All the mask layers of a CBIC are customized and are unique to a particular customer.

In a full CUSTOM ASIC, an engineer designs some or all of the logic cells, circuits or layout SPECIFICALLY for ONE ASIC. It makes sense to take this approach only if there are no suitable existing cell LIBRARIES available that can be USED for the entire design.

In a full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout specifically for one ASIC. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design.

1. Full custom ASICs 

2. Semi-custom ASICs:

• Standard cell based ASICs. 
• GATE-array based ASICs.

3. Programmable ASICs: 

• Programmable LOGIC DEVICE (PLD).
• FIELD Programmable Gate Array (FPGA).

1. Full custom ASICs 

2. Semi-custom ASICs:

3. Programmable ASICs: 

1. BLOCKING ASSIGNMENT 
2. Non-blocking assignment

• INPUT PORT Input 
• OUTPUT port Output 
• BIDIRECTIONAL port INOUT

No ELSE statement:

SYNTAX: if ([expression]) true – statement; 

One else statement: 

Syntax: if ([expression]) true – statement; else false-statement; 

Nested if-else-if:

Syntax:

• if ([expression1]) true statement 1; 
• else if ([expression2]) true-statement 2;
• else if ([EXPRESSION3]) true-statement 3; 
• else default-statement; 

The [expression] is EVALUATED. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

No else statement:

Syntax: if ([expression]) true – statement; 

One else statement: 

Syntax: if ([expression]) true – statement; else false-statement; 

Nested if-else-if:

Syntax:

The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

1. An initial block executes once in the simulation and is USED to set up initial CONDITIONS and step-by-step data FLOW.
2. An always block executes in a loop and REPEATS during the simulation.

Verilog supports basic logic GATES as predefined primitives. Primitive logic function keyword PROVIDES the basics for structural modeling at gate level. These primitives are INSTANTIATED like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, XNOR, and buf (non-inverting DRIVE buffer).

Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provides the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf (non-inverting drive buffer).

Methods of TIMING control: 

1. DELAY-based timing control 
2. Event-based timing control 
3. Level-sensitive timing control

TYPES of delay-based timing control: 

1. REGULAR delay control 
2. Intra-assignment delay control 
3. ZERO delay control 

Types of event-based timing control: 

1. Regular event control 
2. Named event control 
3. Event OR control 
4. Level-sensitive timing control

Methods of timing control: 

Types of delay-based timing control: 

Types of event-based timing control: 

1. CHANNELED GATE arrays 
2. Channel LESS gate arrays 
3. Structured gate arrays

Verilog supports four levels for the values needed to DESCRIBE hardware referred to as value SETS.

Value levels Condition in hardware CIRCUITS:

• 0 Logic zero, false condition 
• 1 Logic one, true condition 
• X Unknown logic value 
• Z High IMPEDANCE, floating state

Verilog supports four levels for the values needed to describe hardware referred to as value sets.

Value levels Condition in hardware circuits: