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Identifiers are names of modules, variables and other OBJECTS that we can reference in the design. Identifiers consists of upper and LOWER CASE letters, digits 0 through 9, the underscore CHARACTER(_) and the dollar sign($). It must be a single group of characters. EXAMPLES: A014, a, b, in_o, s_out.

Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters. Examples: A014, a, b, in_o, s_out.

VERILOG allows switch-level modeling that is BASED on the behavior of MOSFETs. DIGITAL circuits at the MOS-transistor level are described USING the MOSFET switches.

Verilog allows switch-level modeling that is based on the behavior of MOSFETs. Digital circuits at the MOS-transistor level are described using the MOSFET switches.

Structural modeling describes a digital logic networks in TERMS of the components that make up the system. Gate-level modeling is based on using PRIMITIVE logic gates and specifying how they are wired TOGETHER.

Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

1. Gate-level MODELING 
2. Data-flow modeling 
3. Switch-level modeling 
4. BEHAVIORAL modeling

Verilog is a general PURPOSE hardware descriptor language. It is SIMILAR in syntax to the C programming language. It can be USED to MODEL a DIGITAL system at many levels of abstraction ranging from the algorithmic level to the switch level.

Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.

Some of the IMPORTANT CAD tools are: 

1. LAYOUT EDITORS 
2. Design Rule checkers (DRC)
3. Circuit extraction

Some of the important CAD tools are: 

There are two components that establish the amount of power dissipated in a CMOS circuit.

These are:

1. STATIC dissipation due to LEAKAGE CURRENT or other current DRAWN continuously from the power supply.
2. Dynamic dissipation due to.

• Switching transient current.
• Charging and discharging of load CAPACITANCES.

There are two components that establish the amount of power dissipated in a CMOS circuit.

These are:

Delay time, TD is the time difference between input TRANSITION (50%) and the 50% output level. This is the time TAKEN for a logic transition to PASS from input to output.

Delay time, td is the time difference between input transition (50%) and the 50% output level. This is the time taken for a logic transition to pass from input to output.

FALL TIME, TF is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

Rise TIME, TR is the time taken for a WAVEFORM to rise from 10% to 90% of its steady-state VALUE.

Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

Latch up is a condition in which the PARASITIC components give RISE to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during FABRICATION is necessary to avoid this problem.

Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.

The current between DRAIN and SOURCE terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually MODULATED by the applied VDS, increasing VDS causes the depletion region at the drain junction to GROW, REDUCING the length of the effective channel.

The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.

The THRESHOLD voltage, VT for a MOS transistor can be DEFINED as the voltage applied between the GATE and the source of the MOS transistor below which the drain to source CURRENT, IDS effectively drops to zero.

The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

CMOS Technology:

Low STATIC POWER DISSIPATION. High input impedance (low drive current). Scalable threshold voltage. High noise margin. High packing density. High delay sensitivity to load (FANOUT limitations). Low output drive current. Low gm (gm a VIN). Bidirectional capability. A near ideal switching device

Bipolar technology:

High power dissipation. Low input impedance (high drive current). Low voltage swing LOGIC. Low packing density. Low delay sensitivity to load. High output drive current. High gm (gm an eVin). High ft at low current. Essentially unidirectional.

CMOS Technology:

Low static power dissipation. High input impedance (low drive current). Scalable threshold voltage. High noise margin. High packing density. High delay sensitivity to load (fanout limitations). Low output drive current. Low gm (gm a VIN). Bidirectional capability. A near ideal switching device

Bipolar technology:

High power dissipation. Low input impedance (high drive current). Low voltage swing logic. Low packing density. Low delay sensitivity to load. High output drive current. High gm (gm an eVin). High ft at low current. Essentially unidirectional.

• GREEN – n-diffusion
• RED- POLYSILICON
• Blue –metal
• YELLOW- implant
• Black-contact areas.

• It can be DRAWN MUCH easier and faster than a complex LAYOUT.
• These are especially IMPORTANT tools for layout built from large cells.

It is used to CONVEY information through the use of color code. ALSO it is the CARTOON of a chip LAYOUT.

It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.

• N-diffusion
• P-diffusion
• POLYSILICON
• METAL

• CUTOFF REGION 
• NON- SATURATED Region
• Saturated Region

N- CHANNEL transistors has greater switching speed when compared TP PMOS transistors.

N- Channel transistors has greater switching speed when compared tp PMOS transistors.

A DEVICE connected so as to pull the output VOLTAGE to the upper supply voltage USUALLY VDD is called pull up device.

A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device.

A device CONNECTED so as to PULL the OUTPUT voltage to the lower supply voltage usually 0V is called pull down device.

A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down device.

Transistors with Channel length less than 3- 5 MICRONS are termed as Short channel devices. With short channel devices the RATIO between the lateral & vertical dimensions are reduced.

Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short channel devices the ratio between the lateral & vertical dimensions are reduced.

To OBTAIN the functional RELATIONSHIP among the terminal electrical VARIABLES of the DEVICE that is to be modeled.

To obtain the functional relationship among the terminal electrical variables of the device that is to be modeled.

• Low POWER Dissipation 
• HIGH Packing DENSITY 
• Bi DIRECTIONAL capability

Additional MASKS defining P BASE region:

• N Collector area
• Buried SUB collector (SCCD) 
• Processing steps in CMOS process

Additional masks defining P base region:

It is the COMBINATION of BIPOLAR TECHNOLOGY & CMOS technology.

It is the combination of bipolar technology & CMOS technology.

• No Latch-up.
• DUE to ABSENCE of BULKS transistor STRUCTURES are denser than bulk SILICON.

• Tub FORMATION
• Thin-oxide CONSTRUCTION
• Source & DRAIN Implantation 
• CONTACT cut definition 
• Metallization.

• p-well PROCESS
• n-well process
• Silicon-On-Insulator Process
• TWIN- TUB Process

If a LARGE Vds is applied this voltage with DEPLETE the Inversion layer. This Voltage effectively pinches off the CHANNEL NEAR the drain.

If a large Vds is applied this voltage with deplete the Inversion layer. This Voltage effectively pinches off the channel near the drain.

The DEVICE that CONDUCT with ZERO GATE BIAS.

The Device that conduct with zero gate bias.

The DEVICE that is NORMALLY cut-off with ZERO GATE BIAS.

The device that is normally cut-off with zero gate bias.

DRAIN, SOURCE & GATE

Drain, Source & Gate

N-type TRANSISTORS & p-type transistors.

N-type transistors & p-type transistors.

DRY & WET OXIDATION

Dry & Wet Oxidation

• Crystal GROWTH & doping 
• INGOT trimming & GRINDING
• Ingot slicing 
• WAFER polishing & etching 
• Wafer cleaning.

• Silicon wafer Preparation 
• Epitaxial Growth 
• Oxidation
• Photolithography 
• Diffusion
• ION Implantation
• ISOLATION TECHNIQUE 
• Metallization
• ASSEMBLY processing & Packaging

• More SPECIALIZED CIRCUITS
• APPLICATION SPECIFIC INTEGRATED Circuits (ASICs) 
• Systems-On-Chips

• SIZE is less 
• HIGH SPEED
• Less Power DISSIPATION

• SSI (Small Scale Integration)
• MSI (MEDIUM Scale Integration) 
• LSI (LARGE Scale Integration)
• VLSI (Very Large Scale Integration)