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What Are Gate Primitives? |
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Answer» Verilog supports basic logic GATES as predefined primitives. Primitive logic function keyword PROVIDES the basics for structural modeling at gate level. These primitives are INSTANTIATED like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, XNOR, and buf (non-inverting DRIVE buffer). Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provides the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf (non-inverting drive buffer). |
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