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What Is The Use Of Packages? |
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Answer» In Verilog declaration of data/task/function within modules are specific to the module only. They can't be shared between two modules. Agreed, we can ACHIEVE the same via cross module referencing or by including the files, both of which are known to be not a great solution. The package construct of SystemVerilog aims in solving the above issue. It allows having global data/task/function declaration which can be used across modules. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18.2 of SV LRM 3.1a) The content inside the package can be ACCESSED using EITHER scope resolution operator (::), or using import (with option of referencing PARTICULAR or all content of the package). 01.package ABC; In Verilog declaration of data/task/function within modules are specific to the module only. They can't be shared between two modules. Agreed, we can achieve the same via cross module referencing or by including the files, both of which are known to be not a great solution. The package construct of SystemVerilog aims in solving the above issue. It allows having global data/task/function declaration which can be used across modules. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18.2 of SV LRM 3.1a) The content inside the package can be accessed using either scope resolution operator (::), or using import (with option of referencing particular or all content of the package). 01.package ABC; |
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