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What Is The Need Of Alias In Sv? |
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Answer» The VERILOG has one-way ASSIGN statement is a unidirectional assignment and can CONTAIN delay and STRENGTH change. To have bidirectional short-circuit connection SystemVerilog has added alias statement. The Verilog has one-way assign statement is a unidirectional assignment and can contain delay and strength change. To have bidirectional short-circuit connection SystemVerilog has added alias statement. |
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