• It is used to specify synchronization CHARACTERISTICS of the design
• It Offers a clean way to drive and sample signals
• Provides race-free operation if input skew > 0
• HELPS in testbench driving the signals at the right time
•  Features

- Clock specification
- Input skew,output skew
- CYCLE delay (##)

• Can be declared inside interface,module or program

EXAMPLE :

01.Module M1(ck, enin, din, enout, dout);
02.input ck,enin;
03.input [31:0] din ;
04.output enout ;
05.output [31:0] dout ;
06. 
07.clocking sd @(posedge ck);
08.input #2NS ein,din ;
09.output #3ns enout, dout;
10.endclocking:sd
11. 
12.reg [7:0] sab ;
13.initial begin
14.sab = sd.din[7:0];
15.end
16.endmodule:M1

- Clock specification
- Input skew,output skew
- Cycle delay (##)

Example :

01.Module M1(ck, enin, din, enout, dout);
02.input ck,enin;
03.input [31:0] din ;
04.output enout ;
05.output [31:0] dout ;
06. 
07.clocking sd @(posedge ck);
08.input #2ns ein,din ;
09.output #3ns enout, dout;
10.endclocking:sd
11. 
12.reg [7:0] sab ;
13.initial begin
14.sab = sd.din[7:0];
15.end
16.endmodule:M1