Program block is newly added in SystemVerilog. It serves these PURPOSES

1. It separates testbench from DUT
2. It helps in ensuring that testbench doesn't have any race condition with DUT
3. It provides an entry point for execution of testbench
4. It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.

Having said this the major difference between module and program blocks are

1. Program blocks can't have always block inside them, modules can have.
2. Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
3. Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module 
4. Program blocks get executed in the re-ACTIVE region of scheduling queue, module blocks get executed in the active region
5. A program can call a TASK or function in modules or other programs. But a module can not call a task or function in a program.

Program block is newly added in SystemVerilog. It serves these purposes

Having said this the major difference between module and program blocks are