1.

What Is The Dfference Between Always_combo And Always@(*)?

Answer»

From SystemVerilog LRM 3.1a:-

  1. always_comb get executed once at TIME 0, always @* waits till a change occurs on a signal in the INFERRED sensitivity list
  2. Statement within always_comb can't have blocking timing, event control, or fork-join statement. No such restriction of always @*
  3. Optionally EDA tool might PERFORM additional checks to warn if the behavior within always_comb procedure doesn't represent combinatorial logic
  4. Variables on the left-hand side of assignments within an always_comb procedure, including variables from the contents of a called function, shall not be WRITTEN to by any other processes, whereas always @* permits multiple processes to write to the same variable.
  5. always_comb is sensitive to changes within content of a function, whereas always @* is only sensitive to changes to the arguments to the function.

A small SystemVerilog code snippet to illustrate #5

01.module dummy;
02.logic a, b, c, x, y;
03. 
04.// Example VOID function
05.function void my_xor;
06.input a; // b and c are hidden input here
07.x = a ^ b ^ c;
08.endfunction : my_xor
09. 
10.function void my_or;
11.input a; // b and c are hidden input here
12.y = a | b | c;
13.endfunction : my_xor
14. 
15.always_comb // equivalent to always(a,b,c)
16.my_xor(a); // Hidden inputs are also added to sensitivity list
17. 
18.always @* // equivalent to always(a)
19.my_or(a); // b and c are not added to sensitivity list
20.endmodule

From SystemVerilog LRM 3.1a:-

A small SystemVerilog code snippet to illustrate #5

01.module dummy;
02.logic a, b, c, x, y;
03. 
04.// Example void function
05.function void my_xor;
06.input a; // b and c are hidden input here
07.x = a ^ b ^ c;
08.endfunction : my_xor
09. 
10.function void my_or;
11.input a; // b and c are hidden input here
12.y = a | b | c;
13.endfunction : my_xor
14. 
15.always_comb // equivalent to always(a,b,c)
16.my_xor(a); // Hidden inputs are also added to sensitivity list
17. 
18.always @* // equivalent to always(a)
19.my_or(a); // b and c are not added to sensitivity list
20.endmodule



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