1.

What Is Scope Randomization?

Answer»

Scope randomization ins SYSTEMVERILOG allows assignment of unconstrained or constrained random value to the variable within current scope

01.module MyModule;
02.integer var, MIN;
03. 
04.initial begin
05.MIN = 50;
06.for ( INT i = 0;i begin
07.if( randomize(var) with { var < 100 ; var > MIN ;})
 08.$display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);
09.else
10.$display("Randomization failed");
11.end
12. 
13.$finish;
14.end
15.endmodule

Scope randomization ins SystemVerilog allows assignment of unconstrained or constrained random value to the variable within current scope

01.module MyModule;
02.integer var, MIN;
03. 
04.initial begin
05.MIN = 50;
06.for ( int i = 0;i begin
07.if( randomize(var) with { var < 100 ; var > MIN ;})
 08.$display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);
09.else
10.$display("Randomization failed");
11.end
12. 
13.$finish;
14.end
15.endmodule


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