Related InterviewSolutions

• Which of the following is also known as boundary scan?(a) test pattern(b) JTAG(c) FSM(d) CRCThis question was addressed to me in an internship interview.Question is taken from Testing in portion Validation of Embedded Systems
• Which gate is used in the geometrical representation, if a single event causes hazards?(a) AND(b) NOT(c) NAND(d) ORI have been asked this question by my college director while I was bunking the class.Question is taken from Risk and Dependability Analysis in portion Validation of Embedded Systems
• What is CTL?(a) computational tree logic(b) code tree logic(c) cpu tree logic(d) computer tree logicThe question was posed to me during an interview.I'm obligated to ask this question of Formal Verification in division Validation of Embedded Systems
• What is FTA?(a) free tree analysis(b) fault tree analysis(c) fault top analysis(d) free top analysisI have been asked this question by my school teacher while I was bunking the class.I want to ask this question from Risk and Dependability Analysis in section Validation of Embedded Systems
• Which is a top-down method of analyzing risks?(a) FTA(b) FMEA(c) Hazards(d) DamagesThis question was addressed to me during an internship interview.Origin of the question is Risk and Dependability Analysis topic in division Validation of Embedded Systems
• What does BILBO stand for?(a) built-in logic block observer(b) bounded input bounded output(c) built-in loading block observer(d) built-in local block observerThe question was asked in an internship interview.My question is from Testing in portion Validation of Embedded Systems
• Which of the following is based on fault models?(a) alpha-numeric pattern(b) test pattern(c) bit pattern(d) parity patternThis question was posed to me in an interview for internship.I'd like to ask this question from Testing in section Validation of Embedded Systems
• What is FMEA?(a) fast mode and effect analysis(b) front mode and effect analysis(c) false mode and effect analysis(d) failure mode and effect analysisI had been asked this question during an internship interview.The above asked question is from Risk and Dependability Analysis in chapter Validation of Embedded Systems
• Which gate is used in the graphical representation, if several events cause hazard?(a) OR(b) NOT(c) AND(d) NANDThis question was addressed to me during an online exam.I'd like to ask this question from Risk and Dependability Analysis in chapter Validation of Embedded Systems
• Which model is capable of reflecting the bidirectional transfer of information?(a) switch-level model(b) gate level(c) layout model(d) circuit-level modelThis question was posed to me in a national level competition.I want to ask this question from Risk and Dependability Analysis topic in section Validation of Embedded Systems