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What Are Bi-directional Constraints? |
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Answer» Constraints by-default in SYSTEMVERILOG are bi-directional. That implies that the constraint solver doesn't follow the SEQUENCE in which the constraints are specified. All the variables are LOOKED simultaneously. Even the procedural looking constrains LIKE if ... else ... and -> constrains, both if and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be SOLVED as all the possible solution of (!(a==0) || (b==1)). Constraints by-default in SystemVerilog are bi-directional. That implies that the constraint solver doesn't follow the sequence in which the constraints are specified. All the variables are looked simultaneously. Even the procedural looking constrains like if ... else ... and -> constrains, both if and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) || (b==1)). |
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