Wire are Reg are present in the verilog and system verilog adds one more data type called logic. 

Wire : Wire data type is used in the continuous assignments or ports list. It is treated as a wire So it can not hold a value. It can be driven and read. Wires are used for connecting different MODULES. 

Reg : Reg is a date storage element in system verilog. Its not a actual HARDWARE register but it can store values. Register retain there value until next assignment statement. 

Logic : System verilog added this additional datatype extends the rand EG type so it can be driven by a single driver such as gate or MODULE. The main difference between logic dataype and reg/wire is that a logic can be driven by both continuous assignment or blocking/non blocking assignment.

Wire are Reg are present in the verilog and system verilog adds one more data type called logic. 

Wire : Wire data type is used in the continuous assignments or ports list. It is treated as a wire So it can not hold a value. It can be driven and read. Wires are used for connecting different modules. 

Reg : Reg is a date storage element in system verilog. Its not a actual hardware register but it can store values. Register retain there value until next assignment statement. 

Logic : System verilog added this additional datatype extends the rand eg type so it can be driven by a single driver such as gate or module. The main difference between logic dataype and reg/wire is that a logic can be driven by both continuous assignment or blocking/non blocking assignment.