8086 SYSTEM CONFIGURATION IN MINIMUM MODE:- 

As shown in figure interfacing of 8286 bus transceiver 8284 clock generator , the 8282 latch with 8086 microprocessor in minimum mode . 

• The MN/MX’ pin is mode high to support minimum mode. The 8282 latch is used to DE multiplex the address /Data bus line to separate address and data bus .
• The ALE (Address Latch Enable) Signal is used to latch the address from address and data lines. 
• The 8284 clock generator is used to provide the CLK, READY, signals to the 8086 microprocessor. The 8284 generates the ready signal in synchronization with clock based on input at RDY1 pin. The RDY2 pin is connected in this configuration. 
• The reset the 8086 microprocessor the reset pin remain high for 50ms. 
• The data bus is bidirectional in nature. To create a separate data bus from address/data bus two Intel 8286 bidirectional bus Transceiver is used. 
• DT/R’ and DEN’ signal output of8086 microprocessor or are connected to 8086 as T and OE’ respectively.

8086 SYSTEM CONFIGURATION IN MAXIMUM MODE:- 

As shown in figure the interfacing of 8286 bus transceiver , 8284 clock generator , 8282 latch with 8086 microprocessor in this case the MN/MX’ is made low to support the maximum mode operation. 

• The ALE ,DT/R’ and DEN’ signal are generated by 8288 bus controller. 
• The IOB pin is grounded .it indicates that the 8288 is operating in system bus in which all the signals are active. 
• S2’,S1’,S0’ status signal of 8086 microprocessor are input to the 8288 which decodes them and generates INTA’ , MRDC’ ,IORC’ , IOWC’ , ANWC’, and AIOWC, signals .These signal are used for interfacing the 8086 microprocessor to memory and I/O device.