I have a question why is it that cache memory doesnt need an ADDRESS but DRAM does?ummm does this help

2.27 Cache terminology, what does it mean?
[From: [emailprotected] (Cameron L. Spitzer)]

Why cache improves performance

Today's microprocessors ("uPs") need a faster memory than can be made with economical DRAMS. So we provide a fast SRAM buffer between the DRAM and the uP. The most popular way to set it up is by constructing a "direct mapped cache," which is the only setup I'll describe here.

Generic motherboard cache architecture

The direct mapped cache has three big features:

1. a "data store" made with fast SRAMs,

2 a "tag store" made with even faster SRAMs, and

3. a comparator.

The data store is the chunk of RAM you see in the motherboard price lists. It holds "blocks" or "lines" of data recently used by the CPU. Lines are almost always 16 bytes. The address feeding the cache is simply the least significant part of the address feeding main memory. Each memory location can be cached in only one location in the data store.

There are two "policies" for managing the data store. Under the "write-back" (or "copy-back") POLICY, the master copy of the data is in cache, and main memory locations may be "stale" at times. Under "write-through", writes go immediately to main memory as well as to cache and memory is never "stale."

The tag store mantains one "word" of information about each line of data in the data store.

In a "write-back" or "copy-back" cache, the tag word contains two items:

1. the part of the main memory address that was *not* fed to the data store, and

2. a "dirty" bit.

A write-through cache doesn't need a dirty bit. The tag store is addressed with the most significant address bits that are being fed to the data store. The tag is only concerned with the address bits that are used to select a line. With a 16 byte line, address bits 0 through 3 are irrelevant to the tag.

An example: The motherboard has 32 MB main memory and 256 KB cache. To specify a byte in main memory, 25 bits of address are required: A0 through A24. To specify a byte in data store, 18 bits (A0 through A17) are required. Lines in cache are 16 bytes on 16 byte boundaries, so only A4 through A17 are required to specify a line. The tag word for this system would represent A18 through A24 (plus dirty bit). The tag store in this system would be addressed by A4 through A17, therefore the tag store would require 16 K tag words seven bits wide. The dirty bit is written at different times than the rest of the tag, so it might be housed separately, and this tag store might be built in three 16K X4 SRAMs.
I SMELL homework...Yes, I am sure it is in the textbook.