In the digital circuit shown in figure the flip-flops have set time of 5ns and a worst case delay of 15ns. The AND gate has a delay of 5ns. Maximum possible clock rate for the circuit to operate faithfully is

In the digital circuit shown in figure the flip-flops have set time of

1.	In the digital circuit shown in figure the flip-flops have set time of 5ns and a worst case delay of 15ns. The AND gate has a delay of 5ns. Maximum possible clock rate for the circuit to operate faithfully is
Answer» In the digital circuit shown in figure the flip-flops have set time of $5 n s$ and a worst case delay of $15 n s$ . The AND gate has a delay of $5 n s .$ Maximum possible clock rate for the circuit to operate faithfully is

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In the digital circuit shown in figure the flip-flops have set time of 5ns and a worst case delay of 15ns. The AND gate has a delay of 5ns. Maximum possible clock rate for the circuit to operate faithfully is

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