Related InterviewSolutions

• What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?(a) 15 ns(b) 22 ns(c) 60 ns(d) 88 nsThe question was asked during an online interview.I want to ask this question from Counter Implementation and Applications topic in chapter Counters of Digital Circuits
• A ripple counter’s speed is limited by the propagation delay of __________(a) Each flip-flop(b) All flip-flops and gates(c) The flip-flops only with gates(d) Only circuit gatesThis question was posed to me during an online interview.I need to ask this question from Counter Implementation and Applications topic in division Counters of Digital Circuits
• Which one is a 4-bit binary ripple counter?(a) IC 7493(b) IC 7490(c) IC 7491(d) IC 7492I have been asked this question in homework.The origin of the question is Counter ICs topic in section Counters of Digital Circuits
• A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________(a) 10 kHz(b) 20 kHz(c) 30 kHz(d) 60 kHzThe question was posed to me by my school principal while I was bunking the class.My doubt is from Counter ICs in section Counters of Digital Circuits
• A decimal counter has ______ states.(a) 5(b) 10(c) 15(d) 20I had been asked this question during an online interview.I would like to ask this question from Counters in section Counters of Digital Circuits
• How many types of the counter are there?(a) 2(b) 3(c) 4(d) 5The question was asked in semester exam.My doubt is from Counters topic in chapter Counters of Digital Circuits
• A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________(a) 1.25 kHz(b) 2.50 kHz(c) 160 kHz(d) 320 kHzI had been asked this question during an internship interview.The origin of the question is Up Down Counter in division Counters of Digital Circuits
• An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________(a) Taking the output on the other side of the flip-flops (instead of Q)(b) Clocking of each succeeding flip-flop from the other side (instead of Q)(c) Changing the flip-flops to trailing edge triggering(d) All of the MentionedThis question was posed to me in an interview for job.I'm obligated to ask this question of Up Down Counter topic in portion Counters of Digital Circuits
• The designationmeans that the ________(a) Up count is active-HIGH, the down count is active-LOW(b) Up count is active-LOW, the down count is active-HIGH(c) Up and down counts are both active-LOW(d) Up and down counts are both active-HIGHThe question was asked in a national level competition.Origin of the question is Up Down Counter topic in section Counters of Digital Circuits
• Which is not an example of a truncated modulus?(a) 8(b) 9(c) 11(d) 15The question was posed to me in class test.The doubt is from Up Down Counter topic in section Counters of Digital Circuits